Low-End Memory Subsystem Optimization Process


Jungseok Cho,EE, Sunchon National University, South Korea
Jeongdu Lee,EE, Sunchon National University, South Korea
Doosan Cho,EE, Sunchon National University, South Korea


Traditional memories can be categorized to its characteristics like shortcomings advantages. DRAM and SRAM are volatile memories. SRAMs are faster than DRAMs, but they are used in cache memories because they have low integration and high energy consumption compared to DRAMs. On the other hand, DRAM has a slower processing speed than SRAM, but has high integration and low energy consumption. Since the flash memory is a nonvolatile memory, it is used in portable devices. However, it is slower than DRAM and consumes much energy. Non-volatile memory is a new memory that is attracting attention as the next generation memory. Non-volatile memory is a memory that has both higher integration density than DRAM, and low energy consumption, high-speed operation of SRAM, and non-volatile nature of flash memory, which is advantage of conventional memory. For this reason, it is expected to replace DRAM, flash memory, and hard disk in the future. However, Non-volatile memory is not enough to replace DRAM. In case of using non-volatile memory, higher energy consumption may consume than using DRAM only. To solve this problem, it is necessary to study hybrid memories using DRAM and non-volatile memory together. Hybrid memory can be a solution to the slow processing speed and high energy consumption of the negative effect from non-volatile memory technique.



Energy consumption, Hybrid memory, Embedded system, Nonvolatile memory, Low-end memory subsystemr.


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  • APA:
    Cho,J.& Lee,J.& Cho,D.(2019). Low-End Memory Subsystem Optimization Process. International Journal of Smart Home, 13(2), 11-16. 10.21742/IJSH.2019.13.2.02
  • Harvard:
    Cho,J., Lee,J., Cho,D.(2019). "Low-End Memory Subsystem Optimization Process". International Journal of Smart Home, 13(2), pp.11-16. doi:10.21742/IJSH.2019.13.2.02
  • IEEE:
    [1] J.Cho, J.Lee, D.Cho, "Low-End Memory Subsystem Optimization Process". International Journal of Smart Home, vol.13, no.2, pp.11-16, Oct. 2019
  • MLA:
    Cho Jungseok, Lee Jeongdu and Cho Doosan. "Low-End Memory Subsystem Optimization Process". International Journal of Smart Home, vol.13, no.2, Oct. 2019, pp.11-16, doi:10.21742/IJSH.2019.13.2.02


  • Volume 13, No. 2, 2019
  • ISSN(p):1975-4094
  • ISSN(e):2383-725X
  • Published:Oct. 2019